--
-- VHDL Architecture ARMa_lib.CarryExtend.behav
--
-- Created:
--          by - Administrator.UNKNOWN (ECE-5BF87F3CFF5)
--          at - 01:20:28 10/27/2009
--
-- using Mentor Graphics HDL Designer(TM) 2008.1b (Build 7)
--
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.NUMERIC_STD.all;

LIBRARY ARMa_lib;
USE ARMa_lib.ARMa_types.all;

ENTITY CarryExtend IS
   PORT( 
      COutput : IN     std_logic;
      clk     : IN     std_logic;
      CExt    : OUT    ARMa_word
   );

-- Declarations

END CarryExtend ;

--
ARCHITECTURE behav OF CarryExtend IS
BEGIN
  CExt <= "0000000000000000000000000000000" & COutput after delay_MUX2;
END ARCHITECTURE behav;